סקירה כללית
Job Details Job Description: As an Analog Layout Student Engineer, you will work closely with Analog Design Engineers to translate electrical schematics into physical representations on silicon. You will be responsible for creating high-quality layouts for analog and mixed-signal blocks while considering non-ideal effects like parasitics, matching, and noise. Key Responsibilities * Block-Level Layout: Design and verify physical layouts for circuits. * Physical Verification: Run and debug DRC (Design Rule Check), LVS (Layout Vs. Schematic), and Antenna checks using industry-standard tools (e.g., Calibre, Assura). * Parasitic Awareness: Perform RC extraction and work with designers to minimize unwanted resistance and capacitance that could degrade circuit performance. * Matching & Isolation: Implement techniques like common-centroid and interdigitation to ensure transistor matching and use guard rings to prevent latch-up and noise coupling. Qualifications * Education: 3rd‑year B.Sc. student or 1st‑year M.Sc. student in Electrical & Electronics Engineering. * Theoretical Knowledge: Solid understanding of CMOS fabrication processes and semiconductor physics. * Tool Familiarity: Basic exposure to EDA tools (Cadence Virtuoso, Synopsys Custom Compiler, or Mentor Graphics). * Detail Oriented: A "pixel-perfect" mindset—layout requires extreme precision and patience. * Availability: Ability to work at least 20 hours per week (flexible around exam periods). Job Type Student / Intern (Fixed Term) Shift Shift 1 (Israel) Primary Location: Haifa, Israel Additional Locations: Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
דרישות המשרה
* Block-Level Layout: Design and verify physical layouts for circuits. * Physical Verification: Run and debug DRC (Design Rule Check), LVS (Layout Vs. Schematic), and Antenna checks using industry-standard tools (e.g., Calibre, Assura). * Parasitic Awareness: Perform RC extraction and work with designers to minimize unwanted resistance and capacitance that could degrade circuit performance. * Matc
